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Espressif Systems /ESP32-P4 /AXI_DMA /MISC_CONF

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Interpret as MISC_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AXIM_RST_WR_INTER)AXIM_RST_WR_INTER 0 (AXIM_RST_RD_INTER)AXIM_RST_RD_INTER 0 (ARB_PRI_DIS)ARB_PRI_DIS 0 (CLK_EN)CLK_EN

Description

MISC register

Fields

AXIM_RST_WR_INTER

Set this bit then clear this bit to reset the internal axi_wr FSM.
AXIM_RST_RD_INTER

Set this bit then clear this bit to reset the internal axi_rd FSM.
ARB_PRI_DIS

Set this bit to disable priority arbitration function.
CLK_EN

1’h1: Force clock on for register. 1’h0: Support clock only when application writes registers.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data